1. Field of the Invention
The present invention generally relates to semiconductor memory modules. More specifically, the present invention relates to structures and methods associated with an memory module with optical interconnect that enables scalable high-bandwidth memory access.
2. Related Art
A widely-accepted tenet of Moore's Law states that the number of transistors that fit in a square inch of integrated circuitry approximately doubles every two years. For over three decades, technological advances have kept pace with Moore's Law and in doing so have helped to drive processor performance to new heights. Processor manufacturers have exploited the additional circuitry made possible by these advances to build complex processors that support increasing clock frequencies and instruction-level parallelism. Today, such processors accelerate a single instruction pipeline by employing multi-gigahertz frequencies and a variety of sophisticated mechanisms and techniques, such as large caches, superscalar designs, out-of-order execution, deep pipelines, and speculative pre-fetching.
While processor speeds have doubled every two years, memory speeds have only doubled every six years. This growing disparity results from memory suppliers focusing on design objectives based on density and cost rather than on speed. The growing disparity between processor and memory access speeds is presently causing memory latency to dominate application performance. Processors are frequently left idle while waiting for memory accesses to return data, which largely mitigates the performance improvements made possible by increasing processor clock rates. Some processors are configured to access multiple banks of interleaved memories in parallel to increase memory bandwidth. However, because each parallel memory channel consumes a large number of pins, simply increasing the number of channels supported by a memory controller can significantly increase system cost.
Fully-buffered memory technology can replace such multi-pin parallel memory channels with high-speed point-to-point serial interfaces, but such techniques are limited to short distances, and the number of connections is still proportional to the number of desired memory channels.
Hence, what is needed are structures and methods that enable scalable high-bandwidth memory access without the above-described problems.